FIG. 9 shows a circuit proposed as a circuit for simultaneously increasing the withstand voltage of a current driving output terminal and the ESD tolerance of the current driving output terminal in a semiconductor device such as an LED driver IC (for example, see Patent document 1). The following will describe the circuit shown in FIG. 9.
N-channel MOS transistors 101 and 102 compose a current mirror circuit. The drain of the N-channel MOS transistor 101 composing the current mirror circuit is connected to a constant current source 104 and the drain of the N-channel MOS transistor 102 is connected to the emitter of an NPN bipolar transistor 105. Hereinafter, the NPN bipolar transistor 105 will be simply referred to as the NPN transistor 105. A constant voltage source 103 acts as the current supply source of the constant current source 104.
The collector of the NPN transistor 105 connected to the N-channel MOS transistor 102 is connected to a current driving output terminal 106, and the base of the NPN transistor 105 is connected to a constant voltage source 107. In this way, the N-channel MOS transistor 102 and the NPN transistor 105 are cascoded and the NPN transistor 105 is used as a so-called cascode transistor. The collector of the NPN transistor 105 has a withstand voltage higher than the drain withstand voltage of the N-channel MOS transistor, and the NPN transistor 105 increases the withstand voltage of the output terminal 106. Hereinafter, the current driving output terminal 106 will be simply referred to as the output terminal 106.
The source of the N-channel MOS transistor 101 is connected to the drain of an N-channel MOS transistor 108. The source of the N-channel MOS transistor 108 is grounded. Further, the gate of the N-channel MOS transistor 108 is connected to a constant voltage source 109.
The source of the N-channel MOS transistor 102 is connected to the drain of an N-channel MOS transistor 110. The source of the N-channel MOS transistor 110 is grounded. Further, a pulse is supplied to the gate of the N-channel MOS transistor 110 and controls the on/off of current passing through the output terminal 106, that is, the on/off of the emitter current of the NPN transistor 105.
A drain-to-source resistance value obtained when the N-channel MOS transistor 110 is turned on is set equal to the drain-to-source resistance value of the N-channel MOS transistor 108. Thus it is possible to increase the output current accuracy of the current mirror circuit made up of the N-channel MOS transistors 101 and 102, that is, the accuracy of current passing through the output terminal 106.
An ESD protection circuit 111 is connected to the junction of the emitter of the NPN transistor 105 and the drain of the N-channel MOS transistor 102. The ESD protection circuit 111 is made up of an N-channel MOS transistor. To be specific, the drain of the N-channel MOS transistor is connected to the junction of the emitter of the NPN transistor 105 and the drain of the N-channel MOS transistor 102, and the gate and source of the N-channel MOS transistor are both grounded.
By using the ESD protection circuit 111 made up of the element having a breakdown voltage close to the breakdown voltages of the N-channel MOS transistors 102 and 110, the N-channel MOS transistors 102 and 110 connected to the output terminal 106 can be protected from ESD (electrostatic discharge). This is because ESD having been applied to the output terminal 106 and passed through the NPN transistor 105 can be released to the ESD protection circuit 111.
The N-channel MOS transistors 101, 102, 108, and 110 the constant voltage sources 103, 107, and 109, the constant current source 104, the NPN transistor 105, and the N-channel MOS transistor composing the ESD protection circuit 111 are integrated on the same semiconductor substrate 112.
In order to increase the withstand voltage of the current driving output terminal and simultaneously protect from ESD the N-channel MOS transistors connected to the current driving output terminal, the foregoing circuit is provided in a semiconductor device. In other words, the semiconductor device includes the circuit configured such that the NPN bipolar transistor acting as a cascode transistor is interposed between the N-channel MOS transistor and the current driving output terminal and the drain of the N-channel MOS transistor having the grounded gate and source is connected to a path between the NPN bipolar transistor and the N-channel MOS transistor.
However, the semiconductor device configured thus has a problem as will be described below. The N-channel MOS transistor composing the ESD protection circuit 111 has a long channel width because the longer the channel width, the larger the ESD tolerance. Thus a parasitic capacitance increases on the drain of the N-channel MOS transistor composing the ESD protection circuit 111. For this reason, the response speed of current passing through the output terminal 106 decreases relative to the pulse which is supplied to the gate of the N-channel MOS transistor 110 to control the on/off of current passing through the output terminal 106.
Patent document 1: Japanese Patent Laid-Open No. 2007-336262